The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. Below is the realisation in Galois and Fibonacci structures for the same feedback configuration. If any of the tap coefficient is a value other than 1 or 0, they become Non Linear Shift registers. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. These two SR structures are called Linear Feedback Shift Registers (LFSR) if their tap coefficients are only 1 or 0. Sensitive data is also part of our everyday life. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. An Introduction to Cryptography and Linear Feedback Shift Registers Magdalena Stenius All around us data is transferred faster than ever. In this paper, an enhanced BS-LFSR for low power application is proposed. Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance.
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